In recent years, mounting boards including a substrate and electronic components such as a semiconductor integrated circuit mounted on the substrate have been used in various electronic devices. For example, electronic components such as an application specific integrated circuit (ASIC) chip have integrated functions and thus have many input/output terminals. In such an electronic component having many input/output terminals, a so-called “ball grid array (BGA)” of many solder balls (solder bumps) is used as a terminal configuration in order to reduce the mounting area. Examples of such an electronic component include electronic components including memories such as a dynamic random access memory (DRAM). Not only data input/output signals but also a reference voltage used in a DRAM is input to such an electronic component. The reference voltage is a direct current (DC) voltage used as a threshold in the DRAM. Therefore, the fluctuation of the reference voltage due to noise or the like causes malfunction of the DRAM. Thus, as a technique of reducing noise contained in the reference voltage, a capacitor is connected between a ground terminal and a terminal of the electronic component to which the reference voltage is input. Here, in many electronic components, grounded solder balls are disposed in the inner part of the array. In this case, if a capacitor is also mounted on the main surface of the substrate on which the electronic component is mounted, the distance between the terminals of the capacitor and the grounded solder balls of the electronic component are long. The line impedance between the capacitor and the electronic component increases as the distance increases, resulting in a decrease in the noise reduction effect of the capacitor.
There has been proposed a technique of mounting a capacitor on a surface of a substrate opposite to a surface thereof on which an electronic component is mounted and connecting the capacitor to the electronic component by a via wiring (see, for example, Patent Literature (PTL) 1). This technique attempts to reduce the distance between the capacitor and the electronic component so as to reduce the line impedance between the capacitor and the electronic component.